The design of a programmable convolutional encoder using VHDL and an FPGA

Convolutional encoding is a Forward Error Correction (FEC) technique used in continuous one-way and real time communication links. It can provide substantial improvement in bit error rates so that small, low power, inexpensive transmitters can be used in such applications as satellites and hand-held communication devices. This thesis documents the development of a programmable convolutional encoder implemented in a Field Programmable Gate Array (FPGA) from Xilinx, Inc., called the XC3064 Logic Cell Array (LCA). The encoder is capable of coding a digital data stream with any one of 39 convolutional codes. Because the LCA is used for the hardware implementation, the design can be changed or expanded conveniently in the lab. In particularly flexible systems, several encoder designs can be stored in the system RAM, each one being downloaded into the LCA under different circumstances. The encoder has a simple microprocessor interface, a register file for storage of code parameters, a test circuit, and a maximum bit rate of about 15 Mbits/s. Special design techniques like one-hot state assignment, pipelining, and the use of redundant states are employed to tailor the hardware to the LCA architecture Other ways to improve the output bit rate are suggested. The VHSIC Hardware Description Language (VFIDL) is used to model abstract behavior and to define relationships between building blocks before the hardware implementation phase.